The present invention relates to a method and apparatus for converting a PWM (pulse width modulation) signal to an analog output signal. PWM signals have a duty cycle which is the ratio of the time that the pulse is on to the period of the pulse width modulated signal, as determined by the PWM frequency. The duty cycle must often be converted to an analog signal to control an analog device, for example, a motor such as the motor of a blower structure in an automobile.
There are known methods to accomplish this. In one existing system, a division operation is implemented. To decode the PWM signal, a mathematical division operation is performed. Such a system measures the PWM signal period and the low level signal time and does a division of the former by the total period (sum of high and low level times) to determine the duty cycle value. However, designing a division operation in silicon is often difficult and complex.
Another system uses a phase locked and loop (PLL). However, the implementation of a PLL is also complex.
Another simpler solution is an RC (resistor-capacitor) network. This solution is very simple but the RC value must be tailored to the specific PWM frequency and thus does not provide a universal solution.
Accordingly, it is an object of the invention to provide a system for converting a PWM signal to an analog output signal and in particular, a system for converting the PWM duty cycle value to an analog signal and which is independent of input PWM frequency as well as any internal clock signal frequency variations.